Trainings and Consulting/Advice for Functional Verification of SOC Designs

Ramdas is very approachable and a brilliant design verification engineer who worked in my group in Intel. Very skilled and innovative at solving complex problems. He is a quick learner and would be an asset to any any group he joins.

Ramdas is a System Verilog expert. He have extensive experience in functional verification who can guide you in any verification bottlenecks. His skills in developing state of the art verification environment are amazing.

Ramdas is an *exceptionally* talented senior design verification engineer. He can understand a very complex design, put together a thorough verification testplan, and execute the testplan to schedule. Ramdas often diagnoses bugs and identifies the problem down to the line or lines of RTL in question. He is proactive in scheduling reviews, and has excellent verbal and written communication styles. It has been a pleasure working with him on the team, and I hope to work with him again in the future.